---
title: "I/O planning"
---

# I/O planning

The I/O planner for iCE40, ECP5, Gowin, AMD, Altera, PolarFire and Lattice Radiant packages, editing the constraints file as you place pins, bank checks, the Quartus periphery plan, and Vivado's Report Noise.

**Open I/O Planner** (from the FPGA Implementation panel or the Command Palette) draws a target's package and lets you place the top's ports on its pins. The constraints file stays the record: every placement is an edit to it.

## Where each package comes from

| Family | Package data | State |
|---|---|---|
| iCE40 | Project IceStorm's chip database | **Verified (Linux)** |
| ECP5 | Project Trellis's I/O database, next to `ecppack` | **Verified (Linux)** |
| Gowin | Apicula's database (read with the Python that `gowin_pack` runs with) | **Verified (Linux)** |
| AMD 7-series | Project X-Ray's `package_pins.csv`, as openXC7 installs it or through `PRJXRAY_DB_DIR` | **Verified (Linux)** |
| Other AMD parts | Vivado itself: an I/O planning design in batch mode, its answer kept in the build folder | **Modelled**, in no kit |
| Altera | The pin report Quartus writes when it fits the design, or the periphery plan (below) before the first fit | **Modelled** (fitter report); periphery plan **kit shipped** |
| Microchip PolarFire | Libero's pin reports | **Kit shipped** |
| Lattice Radiant | The pad report the build writes, so pins show after the first build | **Modelled** on a real Radiant pad report |

## Place pins

- Leads go around a QFN or QFP counterclockwise from pin 1, balls on their grid, and the A and B rings of dual-row QFNs.
- I/O pins are coloured by bank (or by the die's edge where there are no banks), other pins greyed, and clock inputs ringed (iCE40 global networks, ECP5 PCLKT and PLL inputs, Gowin GCLKT and PLL inputs, AMD MRCC, SRCC and GC P sides).
- Each pin's tooltip has its bank, edge, functions, and the port on it with its I/O standard.
- The top's ports are listed with their pins, unplaced first, with a filter.

Select a port, then click a free pin. The planner edits the target's PCF, LPF, CST, XDC, QSF or PDC file as one undoable edit and saves it: the pin changed in place (in an XDC property dictionary the other properties stay), a statement added, or removed with **Unplace**. Edits you make to the file as text show at once.

Checks as you place:

- a taken pin is refused;
- a clock on a pin that is not a clock input is pointed out;
- banks whose ports need different supplies (from their I/O standards: LVCMOS33 and LVCMOS18 cannot share a bank) are reported;
- XDC ports without an IOSTANDARD are named before Vivado's DRC stops on them.

![The I/O planner on an AMD 7-series package, with pins coloured by bank and every port placed](https://neuralinverse.com/docs-images/modules/hdl/io-planner.webp)

## I/O attributes for PolarFire and Radiant

- **PolarFire:** I/O attributes are edited in the PDC, checked against Microchip's PDC Commands Reference Guide; a value the I/O standard does not have (such as a drive strength LVCMOS33 lacks) is flagged. State: **kit shipped**.
- **Radiant:** `IO_TYPE`, `DRIVE`, `PULLMODE` and other attributes are written with `ldc_set_port`, and locations with `ldc_set_location`, in the PDC. The values offered are those Radiant placed in the design, and banks are checked for a common supply. State: **modelled**.

![A Radiant target's package from the build's pad report, a port's I/O attributes, and a bank supply conflict reported](https://neuralinverse.com/docs-images/modules/hdl/radiant-io-planner.webp)

## Quartus periphery plan

**Plan Periphery (Quartus Interface Planner, I/O Assignment Analysis)**, in the I/O planner's bar or the Command Palette, plans a Quartus target's I/O before a full compile with the Fitter's own engine:

1. Analysis & Synthesis runs first when its result is missing or out of date.
2. The target's `.qsf` pins are applied again, then `quartus_fit --plan` runs on Quartus Prime Pro (the Fitter's Plan stage), or `--check_ios` on Standard and Lite (I/O Assignment Analysis), chosen from the release.
3. The planner draws the whole package from the plan's All Package Pins, shows where the Fitter put each port the `.qsf` leaves free (dashed rings), and lists the I/O assignment warnings and the plan's errors.

Placing a port writes `set_location_assignment` through the `.qsf` writer after you confirm the statement. The Fitter's refusals go to Problems on the `.qsf` lines of the ports a message names. The [device view](https://neuralinverse.com/docs/modules/hdl/device-view/) shows the planned I/O and PLLs until the first full fit; PLLs are shown, not placed.

![A MAX 10 revision after Plan Periphery: the package from the plan, ports the settings file leaves free where the Fitter put them, and the Fitter's warnings](https://neuralinverse.com/docs-images/modules/hdl/quartus-periphery-plan.webp)

State: **kit shipped**; parsers tested on a real Quartus Prime Lite 20.1 Fitter report and real pin-conflict messages.

## Report Noise (Vivado)

**Report Noise (Vivado SSN)** runs `report_ssn` on the design open in the target's Vivado session and lists simultaneous switching noise margins by bank and port. It is Vivado's estimate, not sign-off; parts Vivado does not support are refused plainly. State: **kit shipped**.