---
title: "Program the board"
---

# Program the board

Program FPGA Board with openFPGALoader or the vendor programmers, the confirmation and SHA-256 check, configuration memory for Vivado and Quartus, the Radiant chain file, and the Vitis hardware hand-off.

**No board has been programmed in Neural Inverse's tests.** Everything on this page is **modelled** or **kit shipped**: the confirmations, the SHA-256 checks and every programmer's command line are tested with stand-in processes, and the vendor kits run the real programmers on a board when a tester has one. Nothing is verified on Windows.

## Program FPGA Board

**Program FPGA Board** writes the target's bitstream to the board:

| Target | Programmer | Where it writes |
|---|---|---|
| Open flow (`ice40`, `ecp5`, `gowin`, `xc7`) | openFPGALoader, through the target's `board` or `cable` in `hdl.json` | SRAM or flash |
| Vivado (`xilinx`) | Vivado and hw_server, in batch or in the connected Hardware Debug session; openFPGALoader as the alternative | SRAM, or the configuration memory (below) |
| Quartus (`intel`) | `quartus_pgm` with the SOF over JTAG | SRAM |
| Libero (`microchip`) | FlashPro Express with the exported job, on the target's `programmer` or every connected one | The device's non-volatile configuration (PolarFire and the other Microchip families have no SRAM load) |
| Radiant (`lattice`) | `pgrcmd` with the board's chain file (`xcf`) | As the chain file says |

The steps:

1. Build the target.
2. Run **Program FPGA Board**.
3. Read the confirmation: the target, the board or cable, the bitstream with its size, build time and SHA-256, what the write replaces, and any timing failure.
4. Confirm. The bitstream is hashed again after the confirmation; if it changed, nothing is programmed.

There is no silent or automatic programming. Each programming is logged with its hash. Extra openFPGALoader arguments go in `neuralInverse.hdl.program.openFPGALoaderArguments` (for example `--ftdi-serial` and a serial number to choose between boards).

State: **modelled** (openFPGALoader); **kit shipped** (`quartus_pgm`, FlashPro Express, `pgrcmd`, Vivado).

## Radiant chain file

**Radiant: Scan JTAG Chain and Create Chain File** scans the JTAG chain with openFPGALoader and writes Radiant Programmer's `.xcf` chain file after you confirm, for Fast Configuration of SRAM. The target's `xcf` names it. State: **modelled** (scan on a stand-in; the written `.xcf` read back); not run on a board.

## Configuration memory (Vivado)

A release is usually delivered in flash. For a Vivado target:

1. **Choose Configuration Memory** lists the flash parts Vivado offers for the device (`get_cfgmem_parts`), the board file's flash first, and writes the choice into `targets[].configMemory` in `hdl.json`. The Editor never types a part name itself.
2. **Generate Bitstream** then also writes the `.mcs` or `.bin` and `.prm` (`write_cfgmem`, sized from the part's density, interface from `CONFIG_MODE`).
3. **Program Configuration Memory Device** writes the flash; **Verify Configuration Memory Device** verifies it; **Boot FPGA from Configuration Memory** boots the device from it and reads DONE. They run in the connected Hardware Debug session, or in a Vivado batch run against hw_server.

Every write, verify and boot asks you first, naming the file, its SHA-256, the flash part and the device; the hash is checked again after you confirm.

![Choose Configuration Memory: Vivado's flash parts for the device, the board file's flash first](https://neuralinverse.com/docs-images/modules/hdl/choose-configuration-memory.webp)

`configMemory` also takes the interface, format, size, device, mode and the hw_server to use. State: **kit shipped**; parsers tested on a real `write_cfgmem` log and the SP701, AC701 and Arty board files.

### Tandem configuration

A target's `tandem` block (mode and stage bitstreams) has Generate Bitstream write tandem stage bitstreams for PCIe enumeration time. State: **modelled**, in no kit.

## Configuration memory (Quartus)

**Convert Programming Files** writes a `.jic` (and `.rpd`) with `quartus_cpf`, or with `quartus_pfg` on Pro; MAX 10 uses its `.pof`. Flash is programmed with `quartus_pgm`. Each write asks first. State: **modelled**, in no kit.

## Vitis hand-off

**Export Hardware for Vitis** writes the hardware platform (`.xsa`), with or without the bitstream, from the routed checkpoint; a target's `exportHardware` writes it in every build. State: **kit shipped**.

## Libero programming files

Libero builds export the FlashPro Express job and STAPL files with the bitstream (**Libero: Generate Bitstream and Export Job**). State: **kit shipped**.