# Semiconductors and FPGA

> Close timing sooner, on the licences you already hold.

Source: https://neuralinverse.com/industries/semiconductors/

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[Industries / Mobility and devices](https://neuralinverse.com/industries/)

# Close timing sooner, on the tools you already license.

For FPGA, verification and implementation engineers. Your EDA tools and licences stay as they are.

Standards

DO-254 · ISO 26262

Languages

Verilog, SystemVerilog, VHDL

Open tools

Verilator, Icarus, GHDL, Yosys, nextpnr

Vendor tools

Vivado, Quartus, Libero, Radiant

Deployment

Self-hosted, your cloud or air-gapped

What your team gets

## Write, simulate and synthesise without leaving the editor.

Govern features are in use today. Domain modules are pre-release; their state is listed under Tools and formats.

- **Language support:** Verilog, SystemVerilog and VHDL with navigation and diagnostics.
- **Lint and simulation:** Errors in the editor and testbenches with pass or fail per test, waveforms beside the code.
- **Formal and cocotb:** SymbiYosys properties and cocotb testbenches in the Testing view.
- **Synthesis and timing:** Place and route with utilisation and timing reports for iCE40, ECP5, Gowin and AMD 7-series.
- **Vendor flows:** Vivado, Quartus, Libero and Radiant driven in batch mode, with reports in the same views.
- **Bitstreams stay with people:** The HDL and FPGA template denies agents device programming and bitstream edits; timing and pin constraint changes wait for a named approver.

Who uses it

## One environment for every role on the team.

- **FPGA engineers:** Write, lint and simulate RTL with results in the editor.
- **Verification engineers:** Run testbenches and formal properties with pass or fail per test and waveforms beside the code.
- **Implementation engineers:** Synthesise, place and route, and read utilisation and timing.
- **Lab engineers:** Program boards once a change is approved.

Tools and formats

## What the HDL module handles, and how far each is verified.

The module is behind a setting, off by default, and offers itself once in a workspace with HDL sources.

- **FPGA, open flow:** Lint, simulation, cocotb testbenches, formal verification, waveforms, synthesis and place and route. Verified on Linux. Programming a board is not yet run.
- **AMD 7-series without Vivado:** Artix-7, Kintex-7, Spartan-7 and Zynq-7000 fabric built on the open flow. Verified on Linux by building a bitstream; not programmed on a board.
- **Constraint files:** Checked as they are edited against the elaborated design. Verified on Linux for placement constraints; clocks, delays and exceptions are not checked.
- **FPGA, vendor flows:** The vendor tools driven in batch mode, with their messages and timing and utilisation reports in the same views. Kit shipped or modelled: not yet run against the vendor tools.

Domain modules are pre-release. Nothing is verified by a customer yet, and nothing is verified on Windows. Do not rely on a capability for production work until it is verified for your tools, versions and operating system. Product names belong to their owners.

How a change moves

## A person decides before anything leaves the desk.

1.  Propose
    
    An engineer or agent drafts a change to RTL or constraints.
    
2.  Verify
    
    Your tools lint, simulate and build it.
    
3.  Approve
    
    A timing or pin constraint change waits for a named approver.
    
4.  Record
    
    Change, results and approval kept together in the audit record.
    

Standards

## Evidence for your design assurance. The certification is yours.

- **DO-254:** Evidence toward DO-254: each implementation run kept with the commit it came from, and each RTL change with its review and approval.
- **ISO 26262:** Evidence toward ISO 26262: constraint changes reviewed by a named approver, and every change kept with its approval.

Neural Inverse provides evidence toward these standards. Certification stays with your organisation and assessor.

Products used

[Neural Inverse Build →

Editor, Agents and CLI with the domain tools your engineers need.](https://neuralinverse.com/build/)[Neural Inverse Govern →

Policy, approvals and audit for every AI tool your teams use.](https://neuralinverse.com/govern/)

Product names belong to their owners.

Related industries[Avionics](https://neuralinverse.com/industries/avionics/)[Automotive](https://neuralinverse.com/industries/automotive/)[Defence and space](https://neuralinverse.com/industries/defence/)

![](/photos/team.jpg)

## Talk to our team.

Neural Inverse is available by request. We work with your engineering, security and procurement teams from the first conversation.

[Request access](https://neuralinverse.com/contact/?topic=access)[Contact us](https://neuralinverse.com/contact/)