Three major additions to the Firmware environment (Cmd+Alt+F) — hardware instrument panels, J-Link RTT support, and complete clock/linker coverage across all 148 MCU families.

Hardware Instruments

The Instruments tab now connects directly to physical debug and measurement hardware. Four panels, all canvas-based with interactive displays.

Logic Analyzer

Captures and software-decodes digital signals from your target.

Supported hardware:

• Saleae Logic 2 (TCP automation API, port 10430)
• Digilent WaveForms devices

Built-in decoders — no dependency on Saleae's decoder plugins:

• UART / NRZ serial (configurable baud, parity, stop bits)
• I2C (address extraction, ACK/NACK, repeated start)
• SPI (CPOL/CPHA modes, CS framing)

Decoded frames appear in a table below the waveform with timestamps, hex data, and ASCII.

Power Analyzer

Profiles current draw on your target in real time.

Supported hardware:

• Nordic PPK2 (Power Profiler Kit II) — USB VID 1915 / PID C00A
• Joulescope JS110 and JS220

Displays a continuous current graph with automatic µA/mA scaling. Stats bar shows average, min, max, peak current, energy (µJ), and charge (µC).

Oscilloscope

Captures analog waveforms from bench oscilloscopes over LAN.

Supported hardware:

• Siglent SDS800X HD (SCPI over LAN, port 5025)

Auto-discovered via mDNS LXI. Set VOID_SCOPE_HOST=<ip> to bypass discovery for a fixed IP. CRT-style display with Pk-Pk, Mean, and RMS readouts.

Combined Workflows

Pre-built multi-instrument sequences:

• Sleep current regression — PPK2 current measurement correlated with GDB register reads and logic decodes
• I2C NACK hunt — logic trigger on SCL falling, waits for NACK, reports address and data
• Power-on sequence — scope trigger + simultaneous logic capture

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RTT (Real-Time Transfer)

Stream debug output from your MCU over SWD/JTAG with zero CPU overhead — no UART peripheral required.

Requires a J-Link probe. Neural Inverse connects via:

• JLinkExe (preferred) — if JLinkExe is in PATH
• pylink fallback — pip install pylink-square

New agent tools:

Up to 32 channels supported. 10,000-line ring buffer per channel.

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Full MCU Coverage: Clock Constraints + Linker Origins

All 148 MCU families now have validated clock constraint tables and correct linker script origins — no silent fallthrough to STM32 defaults for other vendors.

New clock constraint tables: TM4C, MSP430 (Harvard), XMC1, XMC4, S32K, Apollo, MAX32, CC26xx, BL60x, Nuvoton, STM32C0, STM32H5, STM32MP1, STM32U5, STM32WB, PIC32, PIC24, PIC18, PIC16, RISC-V families, FPGA soft cores

Notable linker fixes:

• Infineon AURIX: PMU cached PFlash at 0xA0000000 (was incorrectly 0x80000000)
• TI MSP430 Harvard: Flash 0xC000, SRAM 0x0200

Codegen catch-alls:

• fw_codegen_clock now emits SDK-specific guidance for unrecognized families instead of generating STM32 RCC code
• fw_codegen_gpio dispatches per architecture (RISC-V GPIO registers, AVR DDR/PORT, PIC LAT/TRIS) instead of defaulting to STM32 HAL

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Related

• Firmware Documentation
• Firmware Contributing Guide

Copyright 2026 Neural Inverse Inc.

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