This page covers the open FPGA flow, which is verified on Linux except where it says otherwise. Timing figures are nextpnr estimates, not sign-off timing. For Vivado, Quartus, Libero SoC and Radiant builds, see Build with Vivado, Quartus, Libero and Radiant. Timing analysis is on Timing analysis and constraints, and programming on Program the board.
Build a target
Open the FPGA Implementation panel and build a target, or run Build FPGA Target. For an open-flow target (ice40, ecp5, gowin, xc7):
- Yosys synthesises the top for the target's family;
- nextpnr places and routes it with the constraints;
- the bitstream is packed with icepack, ecppack or gowin_pack (for
xc7, see below).
Errors and warnings go to Problems at their source line, at the constraint line, at the declaration of an unconstrained port, or at the target in hdl.json. Constraints that name no port of the top are flagged. A design that misses its clock target still gets its bitstream, with each failing clock reported as an error.
Extra arguments: neuralInverse.hdl.implementation.yosysArguments (for example -m and a plugin) and neuralInverse.hdl.implementation.nextpnrArguments (for example --seed 3).
State: verified (Linux) with Yosys and nextpnr for iCE40, ECP5 and Gowin.
The FPGA Implementation panel
For the selected target the panel shows:
- utilisation per resource against the device;
- each clock's maximum frequency and slack against its target (
frequencyinhdl.json); - the critical paths, with their nets linked to the source;
- the cells of each module of the hierarchy (an estimate, from a second synthesis that keeps the hierarchy).
Show FPGA Implementation Report opens the full report. The panel's toolbar also opens Timing Analysis, the I/O Planner, runs and the PLL configuration for the target.
Build history
Each build of a target is remembered with the commit it came from. The panel shows:
- what changed against the previous build (resources, Fmax and slack);
- the messages grouped by kind (the tool's message ID, or the text without names and numbers), with new ones counted and marked in Problems;
- the recent builds.
The ends of critical paths link to the declarations they come from, through the elaborated hierarchy.
State: verified (Linux) on open-flow builds. History of vendor builds is modelled.
AMD 7-series without Vivado (openXC7)
A target of family xc7 (Artix-7, Kintex-7, Spartan-7, Zynq-7000 fabric) builds without Vivado: Yosys's synth_xilinx, nextpnr-xilinx placing and routing on its chip database and writing FASM, then Project X-Ray's fasm2frames and xc7frames2bit writing the bitstream. The chip database and Project X-Ray's database are found next to nextpnr-xilinx, where openXC7 installs them, in neuralInverse.hdl.openxc7.chipdbDirectory, or through PRJXRAY_DB_DIR.
Everything else of the open flow applies: the report, timing analysis, strategies and seeds, the synthesised schematic, the I/O planner from Project X-Ray's package pins, and constraint checks of the XDC.
State: verified (Linux): an Arty A7-35T bitstream built and checked for the 7-series sync word and the part's IDCODE. Not programmed on a board. This is a second path, not a Vivado path.
Configure a PLL
Configure PLL... (from the panel or the Command Palette) gives the board's oscillator frequency and the output frequencies to the family's own calculator, run on your machine:
| Family | Calculator | Outputs |
|---|---|---|
| iCE40 | icepll (Project IceStorm) | One |
| ECP5 | ecppll (Project Trellis) | Up to four, with the phase of the secondary outputs |
| Gowin | gowin_pll (Apicula, which reads the speed grade from the part number) | One |
What the calculator achieved is read from its output: the frequencies reached, the VCO, and requests outside the PLL's range (an ecppll warning is treated as a failure, because it writes a module even then). The module is saved next to the design's Verilog, with a warning when the project's sources do not include it, and the instance that connects it (clock in, clocks out and a locked signal) is offered to copy. nextpnr derives the output clocks' constraints from the input's.
AMD and Altera targets use the vendors' clocking IP instead; see IP, packaging and HLS.
State: verified (Linux) with icepll, ecppll and gowin_pll.
Run strategies and seeds
Run Implementation Strategies... builds a target with the strategies and seeds you choose, each run in its own folder under the build folder's runs:
| Strategy | Open flow | Vivado | Quartus |
|---|---|---|---|
| Default | Yosys and nextpnr defaults | ||
| Timing | ABC9 mapping, placement weighted toward timing and timing-driven rip-up in nextpnr | Performance directives at each step | High performance effort |
| Retiming | ABC's retiming in Yosys | Extra timing optimisation in placement | |
| Area | Two-pass ABC and DSP blocks where the family has them | Area directives | Aggressive area mode |
| Simulated annealing | nextpnr's simulated annealing placer |
Seeds go to nextpnr's placer and to Quartus's fitter; Vivado has none. Open-flow runs go several at once (neuralInverse.hdl.implementation.parallelRuns, default 2); vendor runs go one at a time.
Show Implementation Runs opens the Implementation Runs editor: runs appear as they finish, best first (built, then most slack or fastest slowest clock, then least logic, then quickest), the best marked. Use This Run makes a run the target's build: its bitstream is the one programmed, its report and problems the ones shown, and it joins the build history.
State: verified (Linux) for iCE40 and ECP5, each strategy checked against the installed tools. Vivado and Quartus strategies and seeds, and Libero's placer seed, are modelled (generated Tcl unit-tested, in no kit). Radiant strategies and seeds are on Build with Vivado, Quartus, Libero and Radiant.
Realistic size
The example design (a dual-channel ADC capture and filter pipeline with a safety monitor) builds for ECP5 and for Artix-7 through openXC7. Measurements on designs of tens of thousands of cells have not been made.